1. Field of the Invention
The present invention generally relates to the fields of chemical vapor deposition of silicon dioxide on wafers to be used in integrated circuit technologies. More particularly, the present invention provides a method of pretreating a silicon wafer to decrease the deposition rate of a silicon dioxide film on the silicon nitride pad of the wafer.
2. Description of the Related Art
Traditionally, local oxidation of silicon (LOCOS) structures was the standard in isolation technology for integrated circuit (IC) silicon devices. However, inherent in this technology are problems of lateral expansion of the isolation region in proportion to depth, non-planarity, thinning, and generation of stress induced silicon defects. Non-planarity of surfaces particularly causes depth of focus problems during any subsequent lithographic patterning of the silicon layer. This becomes critical at design geometries of less than 0.35 microns.
Shallow trench isolation (STI) technology represents a superior application of device-level processing over the more standard LOCOS structure. Shallow trench isolation is primarily designed into devices at or below 0.25 microns with selective use occurring at 0.35 microns. Shallow trench isolation provides better trench depth, width control and greater packing density. Isolation areas are defined using photolithography and etch techniques; silicon dioxide (oxide) deposition into the silicon trench is accomplished via tetraethylorthosilicate (TEOS) or high-density plasma (HDP) vapor deposition.
However, shallow trench. isolation structures require a chemical mechanical polishing (CMP) of the oxide overburden o n the wafer after trench fill. Inherent in this procedure. are problems such as excessive trench oxide dishing in the large open areas which requires the use of dummy features or stop layers as preventative measures. More commonly, inverse masking and etching after silicon dioxide deposition is used to decrease the silicon dioxide thickness on active areas. When CMP is performed subsequent to inverse masking and etching, dishing is reduced compared to a process without inverse masking and etching. However, inverse masking and etching adds cost and complexity to the fabrication process. Failure to detect the CMP endpoint or failure to identify when the active area oxide is completely removed without excessive over-polishing reduces device yield. This increases both process complexity and cost.
Shallow trench isolation (STI) using selective oxide deposition (SELOX) utilizes the differential deposition rates on pad nitride and silicon to achieve good global planarity after the trench fill process. Self-planarizing trench fill occurs when specific conditions are set during chemical vapor deposition (CVI)). Unlike standard shallow trench isolation processes, the self-planarization of the silicon dioxide film can reduce or eliminate the need for dummy features or inverse masking or etching. Thus the SELOX process is markedly less complex than traditional shallow trench isolation methods thereby reducing costs and improving manufacturability of devices.
By delaying deposition of silicon nitride until after deposition on silicon has begun, a thinner film is deposited on silicon nitride relative to silicon. When a delayed nucleation on silicon nitride effectively yields a selective deposition on silicon versus silicon nitride, the selectivity, or film thickness multiple, changes with the desired silicon dioxide thickness. Furthermore, the density of silicon dioxide on silicon nitride deposited by this method is low (porous), making non-destructive measurements of silicon dioxide on silicon nitride impossible. The selective deposition process can be improved upon by making deposition on silicon nitride slower relative to silicon, instead of delaying deposition, which can improve the film thickness multiple. Pretreatment of the wafer results in a constant selectivity value even with a change in film thickness and a concommitant improvement of the quality of the silicon dioxide film on silicon nitride.
The prior art is deficient in the lack of an effective method of decreasing the deposition rate of silicon dioxide on a silicon nitride pad on a wafer to yield a self-planarized oxide layer by pretreating the wafer. The present invention fulfills this long-standing need and desire in the art.
In one embodiment, the present invention provides a method of decreasing a deposition rate of a silicon dioxide film on a silicon nitride pad on a wafer comprising the steps of pretreating the wafer; and vapor-depositing a silicon dioxide film on the wafer; wherein a decreased silicon dioxide deposition rate on the silicon nitride substrate results in a self-planarizing silicon dioxide trench fill on the wafer.
In another embodiment, the present invention provides a method of pretreating a wafer prior to depositing a silicon dioxide film on the wafer comprising the steps of contacting the wafer with a chemical compound selected from the group consisting of hydrogen peroxide, isopropyl alcohol and acetone; and air-drying said chemical compound onto the wafer; wherein the pretreatment of the wafer decreases a deposition rate of a silicon dioxide film on a silicon nitride pad on the wafer.
In yet another embodiment, the present invention provides a method of decreasing the deposition rate of a silicon dioxide film on a silicon nitride pad on a shallow trench isolation silicon wafer comprising the steps of: contacting the wafer with a 30% hydrogen peroxide solution in water; air-drying the hydrogen peroxide solution onto the wafer; and vapor depositing the silicon dioxide on the wafer using ozone-activated tetraethylorthosilicate (O3/TEOS) wherein the vapor deposition is a selective oxidation sub-atmospheric chemical vapor deposition process (SELOX SACVD) and the decreased silicon dioxide deposition rate on the silicon nitride pad results in self-planarizing silicon dioxide trench fill on the wafer.
Other and further aspects, features, and advantages of the present invention will be apparent from the following description of the presently preferred embodiments of the invention given for the purpose of disclosure.